Phase Delay of a SOI Tapered Waveguide
Application ID: 151161
A small building block of integrated photonics, i.e., a Silicon-on-Insulator taper, is considered. For a larger system design, it might be useful to determine the phase delay such a device introduces.
Here, we showcase the layout needed to do it in COMSOL, including a proper Port placement, its phase correction, and manual phase extraction.
We also touch on the way a 3D Frequency Domain simulation correlates with a 2D Boundary Mode Analysis and analytic Transfer Matrix Method considerations. This also provides us with an option to validate the finite element model.
案例中展示的此类问题通常可通过以下产品建模:
您可能需要以下相关模块才能创建并运行这个模型，包括：
建模所需的 COMSOL® 产品组合取决于多种因素，包括边界条件、材料属性、物理场接口及零件库，等等。不同模块可能具有相同的特定功能，详情可以查阅技术规格表，推荐您通过免费的试用许可证来确定满足您的建模需求的正确产品组合。如有任何疑问，欢迎咨询 COMSOL 销售和技术支持团队，我们会为您提供满意的答复。
